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19-0868; Rev 0; 7/07
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer
General Description
The MAX3984 is a single-channel, preemphasis driver with input equalization that operates from 1Gbps to 10.3Gbps. It provides compensation for copper links, such as 8.5Gbps Fibre Channel and 10.3Gbps Ethernet, allowing spans of up to 10m with 24 AWG cable. The driver provides four selectable preemphasis levels, and the selectable input equalizer compensates for up to 10in of FR-4 circuit board material at 10Gbps. The MAX3984 also features SFP-compliant loss-of-signal (LOS) detection and TX_DISABLE. Selectable output swing reduces EMI and power consumption. The MAX3984 is packaged in a lead-free, 3mm x 3mm, 16-pin thin QFN and operates from a 0C to +85C temperature range. Drives Up to 10m of 24 AWG Cable Drives Up to 30in of FR-4 Selectable 1000mVP-P or 1200mVP-P Differential Output Swing Selectable Output Preemphasis Selectable Input Equalization LOS Detection with Built-In Squelch Transmit Disable Hot Pluggable
Features
MAX3984
Applications
8.5Gbps Fibre Channel 10.3Gbps Ethernet Active Cable Assemblies STM-64
PART MAX3984UTE+
Ordering Information
TEMP RANGE PIN-PACKAGE PKG CODE T1633F-3
0C to +85C 16 Thin QFN-EP*
Pin Configuration appears at end of data sheet.
+Denotes a lead-free package. *EP = Exposed pad.
Typical Operating Circuits
DISK ENCLOSURE ACTIVE CABLE ASSEMBLY FABRIC SWTCH 5V RPULLUP 4.7k LOS PE0 LOS PE1 COPPER CABLE DIFFERENTIAL 100 TWIN-AX OUT+ GND OUT0.01F 39 0.01F Rx+ Rx0.01F VCC OR GND OUT+ OUTPE0 PE1 IN_LEV OUT_LEV LOS GND +3.3V IN+ IN22pF 0.01F LOS 22pF 0.01F OUT+ OUT22pF 39 +3.3V VCC IN+ INPE0 0.01F VCC OR GND 39 0.01F 22pF IN+ INGND VCC OR GND 0.01F
+3.3V TX_DISABLE VCC PE0 VCC OR GND 0.01F PE1 IN_LEV OUT_LEV IN+ IN0.01F 10m (24 AWG) UP TO 10Gbps
+3.3V
SWITCH OR SERDES Tx+ Tx-
MAX3984
MAX3984 IN_LEV
OUT_LEV OUT+ OUT-
SWITCH OR SERDES Rx+ Rx-
0.01F
0.01F Tx+ Tx-
5V 4.7k
MAX3984
39
MAX3984
PE1 IN_LEV OUT_LEV
LOS GND TX_DISABLE
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC).................................-0.5V to +4.1V Continuous Output Current Range (OUT+, OUT-) ...............................................-25mA to +25mA Input Voltage Range (IN+, IN-) ..................-0.5V to (VCC + 0.5V) Logic Inputs Range (PE1, PE0, TX_DISABLE, IN_LEV, OUT_LEV) ..........-0.5V to (VCC + 0.5V) LOS Open-Collector Supply Voltage Range (with 4.7k pullup) .........................................-0.5V to +5.5V Storage Ambient Temperature Range (TSTG) ...-55C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
OPERATING CONDITIONS
PARAMETER Supply Voltage Supply Noise Tolerance Operating Ambient Temperature Bit Rate Consecutive Identical Digits (CID) TA NRZ data CID (bits) IN_LEV = high, Figure 2; 4.25Gbps < data rate 10.3Gbps Input Swing (Measured differentially at data source, point A of Figure 2 and 3. Pins LOS and TX_DISABLE are floating.) IN_LEV = high, Figure 2; 1.25Gbps < data rate 4.25Gbps IN_LEV = high, Figure 2; 1.0Gbps data rate 1.25Gbps IN_LEV = low, Figure 3; 1.0Gbps < data rate 10.3Gbps Time to Reach 50% Mark/Space Ratio 360 360 360 100 SYMBOL VCC 1MHz f < 2GHz 0 1.0 CONDITIONS MIN 3.0 TYP 3.3 40 25 8.5 85 10.3 100 1200 1600 mVP-P 2400 360 1 s MAX 3.6 UNITS V mVP-P C Gbps Bits
2
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at TA = +25C, VCC = +3.3V, unless otherwise noted.)
PARAMETER Supply Current Inrush Current Power-On Delay EQUALIZER AND DRIVE SPECIFICATIONS Input Return Loss Input Resistance S11 100MHz to 5GHz Measured differentially (Note 2) Measured differentially at point B in Figure 2; TX_DISABLE = low, OUT_LEV = high, PE1 = PE0 = high Different Output Swing (Notes 3, 4) Measured differentially at point B in Figure 2; TX_DISABLE = low, OUT_LEV = low, PE1 = PE0 = high TX_DISABLE = high, PE1 = PE0 = high Common-Mode Output (AC) (Note 4) Output Resistance Output Return Loss Output Transition Time 20% to 80% Random Jitter (Note 4) R OUT S22 tr, t f Measured at point B in Figure 2; TX_DISABLE = low, OUT_LEV = high (Note 5) OUT+ or OUT-, single-ended 100MHz to 5GHz 20% to 80% (Note 6) Measured at point D in Figure 3 (Note 7) PE1 0 Output Preemphasis Figure 1 (Note 3) 0 1 1 Source to IN OUT to load 3m, 24 AWG Residual Output Deterministic Jitter at 1.0Gbps (Notes 4, 8, and 9) 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG PE1 0 0 1 1 PE0 0 1 0 1 PE0 0 1 0 1 0.02 UI P-P 3.5 6.5 9.5 13 dB 42 50 12 32 40 0.8 85 1000 10 100 115 1300 mVP-P 800 1100 10 25 58 dB ps psRMS mVRMS dB SYMBOL ICC CONDITIONS OUT_LEV = low, TX_DISABLE = low OUT_LEV = high, TX_DISABLE = low Beyond steady state supply current (Note 1) (Note 1) 1 MIN TYP 100 120 MAX 124 148 10 30 UNITS mA mA ms
6-mil, 10in of FR-4
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3
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at TA = +25C, VCC = +3.3V, unless otherwise noted.)
PARAMETER SYMBOL Source to IN CONDITIONS OUT to load 3m, 24 AWG Residual Output Deterministic Jitter at 5.0Gbps (Notes 4, 8, and 9) 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG Source to IN OUT to load 3m, 24 AWG Residual Output Deterministic Jitter at 8.5Gbps (Notes 4, 8, and 9) 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG Source to IN OUT to load 3m, 24 AWG Residual Output Deterministic Jitter at 10Gbps (Notes 4, 8, and 9) 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG Residual Output Deterministic Jitter at 10.0Gbps (Notes 4, 8, and 10) Propagation Delay STATUS OUTPUT: LOS LOS Deassert LOS Assert LOS Hysteresis (Note 4) IN_LEV = high (Note 11) IN_LEV = low (Note 11) IN_LEV = high (Note 11) IN_LEV = high (Note 11) IN_LEV = low (Note 11) 80 20 10 mVP-P 300 100 mVP-P 10in of FR-4 at OUT; no cable; see Figure 3 PE1 0 1 1 1 PE1 0 1 1 1 PE1 0 1 1 1 PE1 0 PE0 1 0 0 1 PE0 1 0 0 1 PE0 1 0 1 1 PE0 0 230 ps 0.18 0.25 UI P-P 0.15 0.20 UI P-P 0.09 0.12 UI P-P MIN TYP MAX UNITS
6-mil, 10in of FR-4
6-mil, 10in of FR-4
6-mil, 10in of FR-4
0.10
UI P-P
4
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = 0C to +85C. Typical values are at TA = +25C, VCC = +3.3V, unless otherwise noted.)
PARAMETER LOS Open-Collector Current Sink LOS Response Time (Note 4) SYMBOL LOS asserted LOS asserted; VOL (Note 12) Time from VIN dropping below deassert level or rising above assert level to 50% point of LOS output transition Rise time or fall time (10% to 90%); pullup supply = 5.5V; external pullup R 4.7k 200 0.4V CONDITIONS MIN 0 1.0 0 25 10 TYP MAX 25 UNITS A mA A s
LOS Transition Time
ns
CONTROL INPUTS: TX_DISABLE, PE0, PE1, OUT_LEV, IN_LEV Logic-High Voltage Logic-Low Voltage Logic-High Current Logic-Low Current VIH VIL I IH I IL Current required to maintain logic-high state at VIH > +2.0V Current required to maintain logic-low state at VIL < +0.8V 2.0 0.8 -150 350 V V A A
Supply voltage to reach 90% of final value in less than 100s, but not less than 10s. Power-on delay interval measured from the 50% level of the final voltage at the filter's device side to 50% level of final current. The supply is to remain at or above 3V for at least 100ms. Only one full-scale transition is permitted during this interval. Aberrations on the transition are limited to less than 100mV. Note 2: IN+ and IN- are single-ended, 50 terminations to (VCC - 1.5V) 0.2V. Note 3: Load is 50 1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps. Note 4: Guaranteed by design and characterization. Note 5: PE1 = PE0 = logic-high (maximum preemphasis), load is 50 1% at each side. The pattern is 11001100 (50% edge density) at 10Gbps. AC common-mode output is computed as: VACCM_RMS = RMS[(VP + VN) / 2) - VDCCM] where: VP = time-domain voltage measured at OUT+ with at least 10GHz bandwidth. VN = time-domain voltage measured at OUT- with at least 10GHz bandwidth. AC common-mode voltage (VACCM_RMS) expressed as an RMS value. DC common-mode voltage (VDCCM) = average DC voltage of (VP + VN) / 2. Note 6: Using 0000011111 or equivalent pattern at 2.5Gbps. PE0 = PE1 = logic-low for minimum preemphasis. Measured within 2in of the output pins with Rogers 4350 dielectric, or equivalent, and 10-mil line width. For transition time, the 0% reference is the steady state level after four zeros, just before the transition, and the 100% reference level is the steady state level after four consecutive logic ones. Note 7: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mVP-P differential swing. IN_LEV = logic-low and PE0 = PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz bandwidth) or equivalent. See Figure 3 for setup. Note 8: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7. Note 9: Input range selection is IN_LEV = logic-high for FR-4 input equalization. Cables are unequalized, Amphenol Spectra-Strip (160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media induced loss and not from clock source modulation. DJ is measured at point D of Figure 2. Note 10: Input range selection is IN_LEV = logic-low. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter point D in Figure 3. The deterministic jitter (DJ) at the output of the transmission line must be from media induced loss and not from clock source modulation. DJ is measured at point D of Figure 3. Note 11: Measured with 101010... pattern at 10Gbps with less than 1in of FR-4 at the input. Note 12: True open-collector outputs. VCC = 0 and the external 4.7k pullup resistor is connected to +5.5V. Note 1: _______________________________________________________________________________________ 5
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
VLOW_PP
VHIGH_PP
VHIGH_PP PE(dB) = 20 log VLOW_PP
Figure 1. TX Preemphasis in dB
TRANSMIT TEST SETUP A SIGNAL SOURCE PCB (FR-4) B
MAX3984
6 MILS IN OUT 6 MILS
24 AWG 100 TWIN-AX
1in L 10in SMA CONNECTORS
L = 2in SMA CONNECTORS
L 1in
6 MILS
OSCILLOSCOPE OR ERROR DETECTOR D
FR-4 4.0 R 4.4 tan = 0.022
Figure 2. Transmit Test Setup (The points labeled A, B, and D are referenced for AC parameter test conditions. Deterministic jitter and eye diagrams measured at point D.)
6
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
RECEIVE TEST SETUP A SIGNAL SOURCE PCB (FR-4) D
MAX3984
6 MILS IN OUT 6 MILS
L = 2in SMA CONNECTORS
L = 10in FR-4 4.0 R 4.4 tan = 0.022
OSCILLOSCOPE OR ERROR DETECTOR SMA CONNECTORS
Figure 3. Receive-Side Test Setup (The points labeled A and D are referenced for AC parameter tests.)
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in of FR-4 at the input, IN_LEV = high, 360mVP-P at input of FR-4, unless otherwise noted.)
DETERMINISTIC JITTER vs. CABLE LENGTH (10.3Gbps)
MAX3984 toc01
DETERMINISTIC JITTER vs. CABLE LENGTH (8.5Gbps)
MAX3984 toc02
DETERMINISTIC JITTER vs. CABLE LENGTH (5Gbps)
0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 PE[1,0] = 11 PE[1,0] = 10 PE[1,0] = 01 PE[1,0] = 00
MAX3984 toc03
1.0 0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 CABLE LENGTH (m) PE[1,0] = 11 10 PE[1,0] = 00 PE[1,0] = 10 PE[1,0] = 01
1.0 0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 PE[1,0] = 10 PE[1,0] = 11 PE[1,0] = 00 PE[1,0] = 01
1.0
12
0
2
4
6
8
10
12
0
2
4
6
8
10
12
CABLE LENGTH (m)
CABLE LENGTH (m)
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7
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in of FR-4 at the input, IN_LEV = high, 360mVP-P at input of FR-4, unless otherwise noted.)
DETERMINISTIC JITTER vs. FR-4 LENGTH (10.3Gbps)
MAX3984 toc04
DETERMINISTIC JITTER vs. FR-4 LENGTH (8.5Gbps)
MAX3984 toc05
DETERMINISTIC JITTER vs. FR-4 LENGTH (5Gbps)
0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 PE[1,0] = 11 PE[1,0] = 10 PE[1,0] = 00 IN_LEV = LOW, 0in OF FR-4 AT THE INPUT PE[1,0] = 01
MAX3984 toc06
1.0 0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 10 20 FR-4 LENGTH (in) PE[1,0] = 11 30 IN_LEV = LOW, 0in OF FR-4 AT THE INPUT PE[1,0] = 00 PE[1,0] = 01 PE[1,0] = 10
1.0 0.9 DETERMINISTIC JITTER (UI) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 PE[1,0] = 11 0 10 20 FR-4 LENGTH (in) 30 IN_LEV = LOW, 0in OF FR-4 AT THE INPUT PE[1,0] = 00 PE[1,0] = 01
1.0
PE[1,0] = 10
0.1 0 40 0 10 20 FR-4 LENGTH (in) 30 40
40
INPUT RETURN LOSS vs. FREQUENCY
MAX3984 toc07
OUTPUT RETURN LOSS vs. FREQUENCY
MAX3984 toc08
TRANSIENT RESPONSE
MAX3984 toc09
0 -5 -10 DIFFERENTIAL S11 (dB) -15 -20 -25 -30 -35 -40 -45 -50 100 1000 FREQUENCY (MHz)
0 -5 DIFFERENTIAL S22 (dB) -10 -15 -20 -25 -30 -35 -40
2.5Gbps K28.7 PATTERN OUT_LEV = HIGH A B C D
A = 3.5dB, PE = 00 B = 6.5dB, PE = 01 C = 9.5dB, PE = 10 D = 13dB, PE = 11 100 1000 FREQUENCY (MHz) 10,000 500ps/div
10,000
VERTICAL EYE OPENING vs. CABLE LENGTH (10.3Gbps)
MAX3984 toc10
VERTICAL EYE OPENING vs. CABLE LENGTH (8.5Gbps)
PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 PE[1,0] = 01 500 PE[1,0] = 10 400 PE[1,0] = 11 300 200 100 0
MAX3984 toc11
VERTICAL EYE OPENING vs. CABLE LENGTH (5Gbps)
PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 PE[1,0] = 01 500 PE[1,0] = 10 400 300 200 100 0 PE[1,0] = 11
MAX3984 toc12
700 PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 PE[1,0] = 01 500 PE[1,0] = 10 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 PE[1,0] = 11
700
700
10
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
CABLE LENGTH (m)
CABLE LENGTH (m)
CABLE LENGTH (m)
8
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer
Typical Operating Characteristics (continued)
(VCC = +3.3V, TA = +25C, PRBS7 + 100 CID pattern is PRBS 27, 100 zeros, 1010, PRBS 27, 100 ones, 0101, OUT_LEV = high, 10in of FR-4 at the input, IN_LEV = high, 360mVP-P at input of FR-4, unless otherwise noted.)
VERTICAL EYE OPENING vs. FR-4 LENGTH (10.3Gbps)
MAX3984 toc13
MAX3984
VERTICAL EYE OPENING vs. FR-4 LENGTH (8.5Gbps)
MAX3984 toc14
VERTICAL EYE OPENING vs. FR-4 LENGTH (5Gbps)
PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 500 400 PE[1,0] = 11 300 200 100 0 IN_LEV = LOW, 0in OF FR-4 AT THE INPUT
MAX3984 toc15
700 PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 PE[1,0] = 01 500
IN_LEV = LOW, 0in OF FR-4 AT THE INPUT
700 PE[1,0] = 00 VERTICAL EYE OPENING (mVP-P) 600 500 400
IN_LEV = LOW, 0in OF FR-4 AT THE INPUT
700
PE[1,0] = 01 PE[1,0] = 10 PE[1,0] = 11 300 200 100 0
PE[1,0] = 01 PE[1,0] = 10
PE[1,0] = 10 400 PE[1,0] = 11 300 200 100 0 0 10 20 FR-4 LENGTH (in) 30 40
0
10
20 FR-4 LENGTH (in)
30
40
0
10
20 FR-4 LENGTH (in)
30
40
10m 24 AWG CABLE ASSEMBLY OUTPUT WITHOUT MAX3984 AT 10.3Gbps
MAX3984 toc16
10m 24 AWG CABLE ASSEMBLY OUTPUT WITH MAX3984 AT 10.3Gbps (PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc17
10m 24 AWG CABLE ASSEMBLY OUTPUT WITHOUT MAX3984 AT 8.5Gbps
MAX3984 toc18
60mVP-P/div
30mVP-P/div
60mVP-P/div
20ps/div
20ps/div
20ps/div
10m 24 AWG CABLE ASSEMBLY OUTPUT WITH MAX3984 AT 8.5Gbps (PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc19
10m 24 AWG CABLE ASSEMBLY OUTPUT WITHOUT MAX3984 AT 5Gbps
MAX3984 toc20
10m 24 AWG CABLE ASSEMBLY OUTPUT WITH MAX3984 AT 5Gbps (PREEMPHASIS, PE[1,0] = 11, OUT_LEV = HIGH)
MAX3984 toc21
60mVP-P/div
30mVP-P/div
20ps/div
50ps/div
30mVP-P/div
50ps/div
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9
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Pin Description
PIN 1 2 3 4, 8, 9, 16 5 6 7 10 11 12 13 NAME VCC1 IN+ INGND OUT_LEV PE1 PE0 OUTOUT+ VCC2 TX_DISABLE FUNCTION Power-Supply Connection for Inputs. Connect to +3.3V. Positive Data Input, CML. This input is internally terminated with 50 . Negative Data Input, CML. This input is internally terminated with 50 . Circuit Ground Output-Swing Control Input, LVTTL with 20k Internal Pullup. Set to TTL high or open for maximum output swing, or set to TTL low for reduced swing. Output Preemphasis Control Input, LVTTL with 10k Internal Pullup. This pin is the most significant bit of the 2-bit preemphasis control. Set high or open to assert this pin. Output Preemphasis Control Input, LVTTL with 10k Internal Pullup. This pin is the least significant bit of the 2-bit preemphasis control. Set high or open to assert this pin. Negative Data Output, CML. This output is terminated with 50 Positive Data Output, CML. This output is terminated with 50 Power-Supply Connection for Output. Connect to +3.3V. Transmitter Disable Input, LVTTL with 10k Internal Pullup. When high or open, differential output is less than 10mVP-P. Set low for normal operation. Loss-of-Signal Detect, Open-Collector TTL Output. Requires an external pullup 4.7k (+5.5V maximum). This output sinks current when the input signal is above the LOS deassert level. To disable squelch pull LOS to ground. Receive Equalization Control Input, LVTTL 40k Internal Pullup. Set to TTL high or open for higher LOS assert/deassert levels and 10in FR-4 compensation. Set to TTL low for lower LOS assert/deassert levels and to bypass the FR-4 equalization. Exposed Pad. For optimal thermal conductivity, this pad must be soldered to the circuit board ground. to VCC2. to VCC2.
14
LOS
15
IN_LEV
--
EP
Detailed Description
The MAX3984 is composed of a receiver, a driver, and an LOS detector with selectable threshold. Equalization is provided in the receiver. Selectable preemphasis and selectable output amplitude are included in the transmitter. The MAX3984 also includes transmit disable control for the output.
Driver
The driver includes four-state preemphasis to compensate for up to 10m of 24 AWG, 100 balanced cable, or 30in of FR-4. The OUT_LEV pin selects the output amplitude. When OUT_LEV is low, the peak-to-peak amplitude is 1000mVP-P. When OUT_LEV is high, the peak-to-peak amplitude is 1200mVP-P.
Receiver
Data is fed into the MAX3984 through a CML input stage and a selectable equalization stage. The fixed equalizer in the receiver corrects for up to 10in of PCB loss on FR-4 material at 10Gbps. The fixed equalizer can be bypassed by setting the IN_LEV pin to a logic-low.
Loss of Signal (LOS)
Input LOS detection is provided. This is an open-collector output and requires an external pullup resistor ( 4.7k). The pullup resistors should be connected from LOS to a supply in the +3.0V to +5.5V range. The LOS output is not valid until power-up is complete.
10
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
VCC2 10k 2 PEO PE1 IN+ CML INFIXED EQUALIZER 0 1 OUT+ PREEMPHASIS CML OUTLOS SIGNAL DETECT VCC2 40k IN_LEV VCC2 10k TX_DISABLE VCC2 20k OUT_LEV LVTTL VCC2 LVTTL VCC2 LVTTL VCC2 LVTTL VCC2 2 VCC2
MAX3984
LIMITER
GND
Figure 4. Functional Diagram
The IN_LEV pin sets the LOS assert and deassert levels. When IN_LEV is LVTTL high or open, the LOS assert threshold is 300mVP-P. When IN_LEV is LVTTL low, the LOS assert threshold is 100mVP-P. TX_DISABLE provides manual control for turning the output off. The MAX3984 has a squelch function that disables the output when there is an LOS condition. To disable the squelch function, connect LOS to ground (see the Squelch section).
Applications Information
Squelch
The MAX3984 can automatically detect an incoming signal and enable or disable the data outputs. To enable squelch, the LOS pin must be connected to a TTL high or V CC with a pullup resistor ( 4.7k). Internally, TX_DISABLE and LOS are connected through an OR-gate to control the CML outputs. The outputs are disabled if LOS asserts. To turn off the squelch function, LOS must be pulled to TTL low. The output can also be disabled when TX_DISABLE is forced high.
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11
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Typical Characteristics at -40C
The MAX3984 is guaranteed to work from 0C to +85C. Table 1 indicates typical performance outside the guaranteed limits.
Table 1. Typical Characteristics at -40C
PARAMETER SYMBOL CONDITIONS Measured differentially at point B in Figure 2; TX_DISABLE = low, OUT_LEV = high, PE1 = PE0 = high Different Output Swing (Note 1) Measured differentially at point B in Figure 2; TX_DISABLE = low, OUT_LEV = low, PE1 = PE0 = high TX_DISABLE = high, PE1 = PE0 = high Common-Mode Output (AC) Random Jitter Measured at point B in Figure 2; TX_DISABLE = low, OUT_LEV = high (Note 2) Measured at point D in Figure 3 (Note 3) Source to IN OUT to load 3m, 24 AWG Residual Output Deterministic Jitter at 1.0Gbps (Notes 4, 5) 6-mil, 10in of FR-4 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG OUT to load 3m, 24 AWG 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG OUT to load 3m, 24 AWG 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG PE1 0 0 1 1 PE1 0 1 1 1 PE1 0 1 1 1 PE0 0 1 0 1 PE0 1 0 0 1 PE0 1 0 0 1 0.2 UI P-P 0.12 UI P-P 0.02 UI P-P MIN TYP 1100 mVP-P 920 3.5 5 0.5 mVRMS psRMS MAX UNITS
Source to IN
Residual Output Deterministic Jitter at 5.0Gbps (Notes 4, 5)
6-mil, 10in of FR-4
Source to IN
Residual Output Deterministic Jitter at 8.5Gbps (Notes 4, 5)
6-mil, 10in of FR-4
12
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1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Table 1. Typical Characteristics at -40C (continued)
PARAMETER SYMBOL Source to IN CONDITIONS OUT to load 3m, 24 AWG 5m, 24 AWG 7m, 24 AWG 10m, 24 AWG PE1 0 1 1 1 PE0 1 0 1 1 0.25 UI P-P MIN TYP MAX UNITS
Residual Output Deterministic Jitter at 10Gbps (Notes 4, 5)
6-mil, 10in of FR-4
Note 1: Load is 50 1% at each side and the pattern is 0000011111 or equivalent pattern at 2.5Gbps. Note 2: PE1 = PE0 = logic-high (maximum preemphasis), load is 50 1% at each side. The pattern is 11001100 (50% edge density) at 10Gbps. AC common-mode output is computed as: VACCM_RMS = RMS[(VP + VN) / 2) - VDCCM] where: VP = time-domain voltage measured at OUT+ with at least 10GHz bandwidth. VN = time-domain voltage measured at OUT- with at least 10GHz bandwidth. AC common-mode voltage (VACCM_RMS) expressed as an RMS value. DC common-mode voltage (VDCCM) = average DC voltage of (VP + VN) / 2. Note 3: Pattern is 0000011111 or equivalent pattern at 10Gbps and 100mVP-P differential swing. IN_LEV = logic-low and PE0 = PE1 = logic-low for minimum preemphasis. Signal transition time is controlled by the 4th-order BT filter (7.5GHz bandwidth) or equivalent. See Figure 3 for setup. Note 4: Test pattern (464 bits): 100 zeros, 1010, PRBS7, 100 ones, 0101, PRBS7. Note 5: Input range selection is IN_LEV = logic-high for FR4 input equalization. Cables are unequalized, Amphenol Spectra-Strip (160-2499-997) 24 AWG or equivalent. Residual deterministic jitter is the difference between the source jitter at point A and the load jitter point D in Figure 2. The deterministic jitter (DJ) at the output of the transmission line must be from media induced loss and not from clock source modulation. DJ is measured at point D of Figure 2.
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13
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Layout Considerations
Circuit board layout and design can significantly affect the performance of the MAX3984. Use good high-frequency design techniques, including minimizing ground inductance and using controlled-impedance transmission lines on the data signals. Power-supply decoupling should also be placed as close as possible to the V CC pins. Always connect all V CC pins to a power plane. Take care to isolate the input from the output signals to reduce feed through.
Exposed-Pad Package
The exposed-pad, 16-pin thin QFN package incorporates features that provide a very low thermal resistance path for heat removal from the IC. The exposed pad on the MAX3984 must be soldered to the circuit board for proper thermal performance. Refer to Maxim Application Note HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information.
Interface Schematics
VCC1 VCC1 - 1.5V RPULLUP 50 IN+ 50 INLVTTL IN VCCX
GND PIN NAME IN_LEV OUT_LEV TX_DISABLE, PE0, PE1 VCCX VCC1 VCC2 VCC2 RPULLUP (k) 40 20 10
GND
Figure 5. IN+/IN- Equivalent Input Structure
VCC2
Figure 7. LVTTL Equivalent Input Structure
LOS 50 50 OUT+ OUTGND
Figure 8. Loss-of-Signal Equivalent Output Structure
GND
Figure 6. OUT+/OUT- Equivalent Output Structure
14 ______________________________________________________________________________________
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer
Typical Operating Circuits (continued)
BLADE BACKPLANE 30in of FR4 UP TO 10Gbps SWTCH LOS PE0 LOS PE1 VCC OR GND 0.01F
MAX3984
+3.3V
+3.3V
TX_DISABLE VCC PE0 VCC OR GND 0.01F PE1 IN_LEV OUT_LEV IN+ IN0.01F +3.3V OUT+ OUT0.01F VCC OR GND PE0 PE1 IN_LEV OUT_LEV LOS GND IN+ INGND OUT+ OUT-
SWITCH OR SERDES Tx+ Tx-
MAX3984
0.01F IN+ IN0.01F
MAX3984
IN_LEV OUT_LEV OUT+
SWITCH OR SERDES Rx+ Rx-
GND
OUT0.01F
0.01F Rx+ Rx-
0.01F OUT+ OUT0.01F
+3.3V VCC IN+ INPE0 LOS
0.01F Tx+ Tx0.01F VCC OR GND
MAX3984
MAX3984
PE1 IN_LEV OUT_LEV
LOS GND TX_DISABLE
______________________________________________________________________________________
15
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Pin Configuration
PROCESS: SiGe Bipolar
IN_LEV
Chip Information
TOP VIEW
GND
+
VCC1 IN+ INGND 1 2 3 4
16
15
14
13
TX_DISABLE 12 VCC2 11 OUT+ 10 OUT9 GND EP* 8 GND
MAX3984UTE
5 OUT_LEV
6 PE1
7 PE0
THIN QFN-EP (3mm x 3mm)
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL OPERATION OF THE MAX3984.
16
______________________________________________________________________________________
LOS
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX3984
MARKING
E E/2
(ND - 1) X e
(NE - 1) X e
D2/2
D/2 D
AAAA
C L
e D2
k
b E2/2
0.10 M C A B
C L
L
E2
0.10 C
0.08 C A A2 A1 L
C L
C L
L
e
e
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
1 2
______________________________________________________________________________________
12x16L QFN THIN.EPS
17
1Gbps to 10Gbps Preemphasis Driver with Receive Equalizer MAX3984
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PKG REF. A b D E e L N ND NE A1 A2 k 0.25 0 0.35
8L 3x3 MIN. NOM. MAX. 0.70 0.25 2.90 2.90 0.75 0.30 3.00 3.00 0.55 8 2 2 0.02 0.20 REF 0.25 0.05 0 0.80 0.35 3.10 3.10 0.75
12L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.45 0.75 0.25 3.00 3.00 0.55 12 3 3 0.02 0.20 REF 0.25 0.05 0 0.80 0.30 3.10 3.10 0.65
16L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.30 0.75 0.25 3.00 3.00 0.40 16 4 4 0.02 0.20 REF 0.05 0.80 0.30 3.10 3.10 0.50 PKG. CODES TQ833-1 T1233-1 T1233-3 T1233-4 T1633-2 T1633F-3 T1633FH-3 T1633-4 T1633-5
EXPOSED PAD VARIATIONS
D2 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 E2 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.225 x 45 0.225 x 45 0.35 x 45 0.35 x 45 JEDEC WEEC WEED-1 WEED-1 WEED-1 WEED-2 WEED-2 WEED-2 WEED-2 WEED-2
0.65 BSC.
0.50 BSC.
0.50 BSC.
NOTES: 1. 2. 3. 4. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm.
5. 6. 7. 8. 9. 10. 11. 12.
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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